[PATCH] D140645: Add tests for atomic bittest with register/memory operands

[Noah Goldstein via Phabricator via llvm-commits]

goldstein.w.n created this revision.
Herald added subscribers: pengfei, hiraditya.
Herald added a project: All.
goldstein.w.n requested review of this revision.
Herald added a project: LLVM.
Herald added a subscriber: llvm-commits.

Transform AtomicRMW logic operations to BT{R|C|S} if only changing/testing a single bit.

This is essentially expanding on the optimizations added on: D120199 <https://reviews.llvm.org/D120199>
but applies the optimization to cases where the bit being changed /
tested is not am IMM but is a provable power of 2.

The only case currently added for cases like:
__atomic_fetch_xor(p, 1 << c, __ATOMIC_RELAXED) & (1 << c)

Which instead of using a `cmpxchg` loop can be done with `btcl; setcc; shl`.

There are still a variety of missed cases that could/should be
addressed in the future. This commit documents many of those
cases with Todos.

1. This is a combination of 2 commits.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140645

Files:
  llvm/include/llvm/IR/IntrinsicsX86.td
  llvm/lib/Target/X86/X86ISelLowering.cpp
  llvm/lib/Target/X86/X86ISelLowering.h
  llvm/lib/Target/X86/X86InstrCompiler.td
  llvm/test/CodeGen/X86/atomic-rm-bit-test.ll