[PATCH] D140602: [RISCV] Add fmin/fmax scalar instructions to isAssociativeAndCommutative

Hsiangkai Wang via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Thu Dec 22 19:28:47 PST 2022


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Follow-up patch of D140530 <https://reviews.llvm.org/D140530>.

We can add FMIN, FMAX to isAssociativeAndCommutative to
increase instruction-level parallelism by the existing MachineCombiner
pass.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140602

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
  llvm/test/CodeGen/RISCV/machine-combiner.ll

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