[PATCH] D137517: [TargetParser] Generate the defs for RISCV CPUs using llvm-tblgen.

Wed Dec 21 19:57:08 PST 2022

craig.topper added a comment.

In D137517#4012298 <https://reviews.llvm.org/D137517#4012298>, @pcwang-thead wrote:

> In D137517#4009175 <https://reviews.llvm.org/D137517#4009175>, @fpetrogalli wrote:
>
>> @pcwang-thead, I addressed some of your comments.
>>
>> The value of `EnumFeatures` is now computed dynamicaly from the
>> `Features` field of the `Processor` class.
>
> Thanks! That sounds great to me!
>
>> As for generating `MArch` out of the `Features` field, @craig.topper
>> pointed me at
>> https://github.com/riscv-non-isa/riscv-toolchain-conventions/issues/11. From
>> the reading of it, it seems that the alphabetical order is enough to
>> build the string that carries `MArch`. Am I missing something?
>
> Currently, I think the alphabetical order is OK. If we relax the checking of arch string someday, there is no doubt that we should change the implementation here too.

The currently accepted order isn’t alphabetical. The single letter extensions have a specific order. The z extensions are ordered by looking up the second letter in the single letter order. If we alphabetize here i don’t think it will be accepted by the frontend.

Repository:
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  https://reviews.llvm.org/D137517/new/

https://reviews.llvm.org/D137517