[PATCH] D140347: TargetLowering: Teach DemandedBits about VSCALE

[Saleem Abdulrasool via Phabricator via llvm-commits]

compnerd updated this revision to Diff 484368.
compnerd added a comment.

Further reduce the test case.  We create the splat and shuffle, offset it by vlenb and return the generated splat.  This reduces down to the minimal assembly sequence that would exhibit the issue.  If we were to accidentally truncate the scale, we would drop the read of `vlenb` and the adjustment for the shuffle.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140347/new/

https://reviews.llvm.org/D140347

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll
  llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll

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