[PATCH] D140347: TargetLowering: Teach DemandedBits about VSCALE
Saleem Abdulrasool via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 20 11:11:26 PST 2022
compnerd updated this revision to Diff 484329.
compnerd added a comment.
Further reduce test case by creating a hand written synthetic test case. We can get away with a 2-iteration unrolled loop avoiding any phi branches. The previous overflow would improperly remove the increment in between the two iterations.
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D140347/new/
https://reviews.llvm.org/D140347
Files:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll
llvm/test/CodeGen/RISCV/vscale-demanded-bits.ll
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