[PATCH] D140287: [AArch64] Combine to UMULL if top bits are known zero

[Dave Green via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3c0c24e0c1d3: [AArch64] Combine to UMULL if top bits are known zero (authored by dmgreen).

Changed prior to commit:
  https://reviews.llvm.org/D140287?vs=483888&id=484240#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140287/new/

https://reviews.llvm.org/D140287

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-dup-ext.ll
  llvm/test/CodeGen/AArch64/aarch64-smull.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D140287.484240.patch
Type: text/x-patch
Size: 9190 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221220/a1014616/attachment.bin>