[PATCH] D140287: [AArch64] Combine to UMULL if top bits are known zero

[Sam Tebbs via Phabricator via llvm-commits]

samtebbs accepted this revision.
samtebbs added a comment.
This revision is now accepted and ready to land.

LGTM



================
Comment at: llvm/lib/Target/AArch64/AArch64ISelLowering.cpp:4587
+
+  // Select UMULL if we can replace the other operand with an extends.
+  if (IsN0ZExt || IsN1ZExt) {
----------------
"extend" or "extends"?


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140287/new/

https://reviews.llvm.org/D140287