[PATCH] D138097: [BOLT][AArch64] Handle adrp+ld64 linker relaxations

Mon Dec 19 15:45:47 PST 2022

maksfb accepted this revision.
maksfb added a comment.
This revision is now accepted and ready to land.

LGTM

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Comment at: bolt/test/AArch64/got-ld64-relaxation.test:1
+// This test checks that ADR+LDR instruction sequence relaxed by the linker
+// to the ADR+ADD sequence is properly reconized and handled by bolt
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yota9 wrote:
> maksfb wrote:
> > Does it make sense to generate a test case with lld similar to x86 GOTPCRELX test in D126747?
> The thing is that the linker will relax it to the adr + nop due to small size of the final binary. Such a case is already handled in skipRelocationProcessAArch64, but for adrp+add case it is better to use pre-built binary
You can make the binary artificially bigger with `.zero/.skip` directives.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D138097/new/

https://reviews.llvm.org/D138097