[PATCH] D140319: [RISCV] Match neg (and x, 1) to two shifts to improve codesize

[Philip Reames via Phabricator via llvm-commits]

reames added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:1244
+// is never compressible since rs1 and rd can't be the same register.
+let Predicates = [IsRV64, HasStdExtC] in {
+def : Pat<(XLenVT (sub 0x0, (and_oneuse GPR:$rs, 0x1))),
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This shouldn't be specific to RV64, but my attempts to write a pattern which used ImmSubFromVLen kept failing type inference.  Any suggestions on how to write such a pattern?


Repository:
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  https://reviews.llvm.org/D140319/new/

https://reviews.llvm.org/D140319