[PATCH] D140319: [RISCV] Match neg (and x, 1) to two shifts to improve codesize

[Philip Reames via Phabricator via llvm-commits]

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The negate operation is never compressible (as the destination and rs1 register must differ).  The two shift versions will be equal size if the input GPR is reused, or smaller if this is the only use of the input.

For clarity, the operation being performed is (select (low-bit-of x), -1, 0).


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D140319

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfo.td
  llvm/test/CodeGen/RISCV/short-foward-branch-opt.ll

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