[PATCH] D140200: [AArch64][InstCombine] Fuse ADD+MUL and SUB+MUL AArch64 instrinsics

[Sander de Smalen via Phabricator via llvm-commits]

sdesmalen added inline comments.


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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1048
 
+template <Intrinsic::ID T, typename Intrinsic::ID M>
 static std::optional<Instruction *>
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nit: Can you give `T` and `M` slightly more descriptive names? :) 


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Comment at: llvm/test/Transforms/InstCombine/AArch64/sve-intrinsic-muladdsub.ll:464
+; CHECK-NEXT:    [[TMP1:%.*]] = tail call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> [[P:%.*]])
+; CHECK-NEXT:    [[TMP2:%.*]] = call fast <vscale x 8 x half> @llvm.aarch64.sve.fmsb.nxv8f16(<vscale x 8 x i1> [[TMP1]], <vscale x 8 x half> [[B:%.*]], <vscale x 8 x half> [[C:%.*]], <vscale x 8 x half> [[A:%.*]])
+; CHECK-NEXT:    ret <vscale x 8 x half> [[TMP2]]
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You can't make the same assumptions for MSB as you can for MAD, because the meaning of this is `%a - (%b * %c)`, which is not equal to `(%b * %c) - %a`.


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  https://reviews.llvm.org/D140200/new/

https://reviews.llvm.org/D140200