[PATCH] D140200: [AArch64][InstCombine] Fuse ADD+MUL and SUB+MUL AArch64 instrinsics

Mon Dec 19 07:08:17 PST 2022

MattDevereau marked 2 inline comments as done.
MattDevereau added inline comments.

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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1079
+// Fold (ADD p c (MUL p a b)) -> (MAD p a b c)
+static std::optional<Instruction *> instCombineSVEVectorMAD(InstCombiner &IC,
+                                                            IntrinsicInst &II) {
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sdesmalen wrote:
> This function looks very similar to instCombineSVEVectorFMLA, I think we could combine them. There are some subtle differences though:
> * Fast-math flags can only be copied if the type is floating-point.
> * MAD is different from MLA in that the result is merged into the multiplicant, not the addend. You could pass a parameter `WriteAddend` that is used like this:
> ```
>   Value *A = II.getOperand(1);
>   Value *Mul = II.getOperand(2);
>   if (!WriteAddend)
>     std::swap(A, Mul);
>   if (!match(Mul, m_Intrinsic<Intrinsic::aarch64_sve_mul>(...))
> ```
> * If you pass in the opcode to test for (in this case `Intrinsic::aarch64_sve_mul`) and the result `Intrinsic::aarch64_sve_mad`, then you could generalise this.
I've reworked `instCombineSVEVectorFMLA` into a function that can handle both the Addend/Not-Addend case which also handles floating-point vectors.

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Comment at: llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp:1499
+    return instCombineSVEVectorAdd(IC, II);
   case Intrinsic::aarch64_sve_fsub:
     return instCombineSVEVectorBinOp(IC, II);
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sdesmalen wrote:
> It would be nice if we could do the same thing for subtracts (fmls/fmsb/mls/msb)
I've added support for these now.

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D140200/new/

https://reviews.llvm.org/D140200