[PATCH] D140206: [RISCV] Omit SRA in case of setlt or setge with zero constant

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/test/CodeGen/RISCV/branch_zero.ll:11
 ; CHECK-NEXT:    slli a0, a0, 48
-; CHECK-NEXT:    srai a0, a0, 48
 ; CHECK-NEXT:    bltz a0, .LBB0_4
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Can you construct a test for GE too?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140206/new/

https://reviews.llvm.org/D140206