[PATCH] D140206: [RISCV] Omit SRA in case of setlt or setge with zero constant

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

In D140206#4001027 <https://reviews.llvm.org/D140206#4001027>, @eklepilkina wrote:

> During fixing this case I had a question why RISCV doesn't use `SimplifySetCC` from common TargetLowering. It seems that there are some cases of combinations that should work for RISCV. I tried to call it, but found cases that crashes compilations on RISCV. Are there any plans to rework this part and reuse some part of foldings from common lowering? It seems that some optimizations can be lost, doesn't it?

It should be called from DAGCombiner both before and after type legalization. I think the issue here is that the setcc is merged into RISCVISD::BR_CC before the sign_extend_inreg is converted to shl+sra.


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https://reviews.llvm.org/D140206