[PATCH] D140046: [PowerPC] Fix up memory ordering after combining BV to a load
Nemanja Ivanovic via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Dec 16 06:58:10 PST 2022
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcb3f415cd201: [PowerPC] Fix up memory ordering after combining BV to a load (authored by nemanjai).
Changed prior to commit:
https://reviews.llvm.org/D140046?vs=483341&id=483527#toc
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D140046/new/
https://reviews.llvm.org/D140046
Files:
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
llvm/test/CodeGen/PowerPC/build-vector-to-ld-chain.ll
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