[PATCH] D140046: [PowerPC] Fix up memory ordering after combining BV to a load

[Eli Friedman via Phabricator via llvm-commits]

efriedma accepted this revision.
efriedma added a comment.

LGTM



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Comment at: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:11500
     return false;
-  EVT VT = LD->getValueType(0);
+  EVT VT = LD->getMemoryVT();
   if (VT.getSizeInBits() / 8 != Bytes)
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nemanjai wrote:
> @efriedma @RKSimon Do you see any issues with switching this? It seems that we should be checking the memory type to determine if loads are consecutive. This is also required in order to use this query for extending loads for PPC.
I think all the existing uses exclude extending loads?  Seems fine.


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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14309
 
   LoadSDNode *LD1 = dyn_cast<LoadSDNode>(FirstLoadOp);
   LoadSDNode *LDL = dyn_cast<LoadSDNode>(LastLoadOp);
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Is LD1 here the same node as LD above?  Could simplify that a bit, maybe.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D140046/new/

https://reviews.llvm.org/D140046