[PATCH] D140046: [PowerPC] Fix up memory ordering after combining BV to a load

[Nemanja Ivanovic via Phabricator via llvm-commits]

nemanjai updated this revision to Diff 483341.
nemanjai added a comment.

Forgot to remove the redundant checks for input chain equality now that I switched to `areNonVolatileConsecutiveLoads()`.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D140046/new/

https://reviews.llvm.org/D140046

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/lib/Target/PowerPC/PPCISelLowering.cpp
  llvm/test/CodeGen/PowerPC/build-vector-to-ld-chain.ll

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