[PATCH] D140046: [PowerPC] Fix up memory ordering after combining BV to a load

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon accepted this revision.
RKSimon added a comment.
This revision is now accepted and ready to land.

LGTM, although its annoying that you can't use SelectionDAG::areNonVolatileConsecutiveLoads somehow.

One minor - nothing to do with this patch, but something that probably should be addressed if you're in the vicinity.



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Comment at: llvm/lib/Target/PowerPC/PPCISelLowering.cpp:14276
     LoadSDNode *LD1 = dyn_cast<LoadSDNode>(PreviousInput);
     LoadSDNode *LD2 = dyn_cast<LoadSDNode>(NextInput);
 
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You're immediately dereferencing dyn_cast<> - these can probably be cast<>? 


Repository:
  rG LLVM Github Monorepo

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https://reviews.llvm.org/D140046