[llvm] ddf2f90 - [EarlyIfConversion] Add target hook to allow for multiple ifcvt iterations.

Hendrik Greving via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 14 13:37:45 PST 2022


Author: Hendrik Greving
Date: 2022-12-14T13:36:20-08:00
New Revision: ddf2f90a48b638fcd7cd1dbeeffec14390fb47b8

URL: https://github.com/llvm/llvm-project/commit/ddf2f90a48b638fcd7cd1dbeeffec14390fb47b8
DIFF: https://github.com/llvm/llvm-project/commit/ddf2f90a48b638fcd7cd1dbeeffec14390fb47b8.diff

LOG: [EarlyIfConversion] Add target hook to allow for multiple ifcvt iterations.

Adds a target hook canPredicatePredicatedInstr(const MachineInstr&) that
assumes an instruction is already predicated and returns true if it can
be predicated again, used by the early if-conversion pass in order to
iterate multiple times on architectures supporting predicate logic.

No test added since there is no upstream target that can take advantage.

Differential Revision: https://reviews.llvm.org/D139981

Added: 
    

Modified: 
    llvm/include/llvm/CodeGen/TargetInstrInfo.h
    llvm/lib/CodeGen/EarlyIfConversion.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/include/llvm/CodeGen/TargetInstrInfo.h b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
index c64e10f10837..f0559b554e51 100644
--- a/llvm/include/llvm/CodeGen/TargetInstrInfo.h
+++ b/llvm/include/llvm/CodeGen/TargetInstrInfo.h
@@ -1464,6 +1464,13 @@ class TargetInstrInfo : public MCInstrInfo {
   /// Returns true if the instruction is already predicated.
   virtual bool isPredicated(const MachineInstr &MI) const { return false; }
 
+  /// Assumes the instruction is already predicated and returns true if the
+  /// instruction can be predicated again.
+  virtual bool canPredicatePredicatedInstr(const MachineInstr &MI) const {
+    assert(isPredicated(MI) && "Instruction is not predicated");
+    return false;
+  }
+
   // Returns a MIRPrinter comment for this machine operand.
   virtual std::string
   createMIROperandComment(const MachineInstr &MI, const MachineOperand &Op,

diff  --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp
index c108f0088d43..e3305ccf1cb8 100644
--- a/llvm/lib/CodeGen/EarlyIfConversion.cpp
+++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp
@@ -321,9 +321,15 @@ bool SSAIfConv::canPredicateInstrs(MachineBasicBlock *MBB) {
       return false;
     }
 
-    // Check that instruction is predicable and that it is not already
-    // predicated.
-    if (!TII->isPredicable(*I) || TII->isPredicated(*I)) {
+    // Check that instruction is predicable
+    if (!TII->isPredicable(*I)) {
+      LLVM_DEBUG(dbgs() << "Isn't predicable: " << *I);
+      return false;
+    }
+
+    // Check that instruction is not already predicated.
+    if (TII->isPredicated(*I) && !TII->canPredicatePredicatedInstr(*I)) {
+      LLVM_DEBUG(dbgs() << "Is already predicated: " << *I);
       return false;
     }
 


        


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