[PATCH] D139965: [RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for SExtWRemoval.
Craig Topper via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Dec 14 10:39:24 PST 2022
This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG3e7dad22f111: [RISCV] Add a bit to TSFlags to mark SignExtendingOpW instructions for… (authored by craig.topper).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D139965/new/
https://reviews.llvm.org/D139965
Files:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h
llvm/lib/Target/RISCV/RISCVInstrFormats.td
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoM.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
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