[PATCH] D139732: [AMDGPU] Add pass to rewrite partially used virtual superregisters after RenameIndependentSubregs pass with registers of minimal size (WIP)

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


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Comment at: llvm/include/llvm/MC/LaneBitmask.h:85-88
     static constexpr LaneBitmask getLane(unsigned Lane) {
       return LaneBitmask(Type(1) << Lane);
     }
+    static constexpr LaneBitmask getLanes(unsigned NumLanes) {
----------------
having "getLane" and "getLanes" is going to be terribly confusing. Needs a different name


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Comment at: llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp:108
+                                             unsigned Size) const {
+  auto R = SubRegs.try_emplace(std::pair(Offset, Size), 0);
+  if (R.second) {
----------------
I think {Offset, Size} should work now


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Comment at: llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp:155
+  LLVM_DEBUG(dbgs() << "  Try shift " << RShift << '\n');
+  BitVector ClassMask(TRI->getNumRegClasses(), true);
+  for (auto &P : SubRegs) {
----------------
Comment what true is?


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Comment at: llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp:162-164
+    if (!SubRegRC)
+      if (!(SubRegRC = TRI->getSubRegisterClass(RC, OldSubReg)))
+        return nullptr;
----------------
```
if (!SubRegRC)
  SubRegRC = ...

if (!SubRegRC)
  return nullptr

```


================
Comment at: llvm/lib/Target/AMDGPU/GCNRewritePartialRegUses.cpp:302-305
+  if (LIS) {
+    LIS->removeInterval(Reg);
+    LIS->createAndComputeVirtRegInterval(NewReg);
+  }
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Can you do better than delete and recreate the liveness? Can we do this before liveness is computed?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139732/new/

https://reviews.llvm.org/D139732