[PATCH] D138508: [TargetLowering] Teach DemandedBits about VSCALE

[Benjamin Maxwell via Phabricator via llvm-commits]

benmxwl-arm updated this revision to Diff 482442.
benmxwl-arm added a comment.

Replaced negation with `~` and added a new test case where this makes a difference.
(Previosuly the redundant `or` in the new test case would not be removed)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138508/new/

https://reviews.llvm.org/D138508

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D138508.482442.patch
Type: text/x-patch
Size: 3925 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20221213/d569a963/attachment.bin>