[PATCH] D138508: [TargetLowering] Teach DemandedBits about VSCALE

Paul Walker via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Tue Dec 13 04:59:22 PST 2022


paulwalker-arm added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp:1140
+    if (Negative)
+      VScaleResultUpperbound = -VScaleResultUpperbound;
+    unsigned RequiredBits = Log2_64(VScaleResultUpperbound) + 1;
----------------
Would this be more accurate as `~`? Also means we don't need to worry about the negation overflowing, which I doubt is a real concern anyway.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138508/new/

https://reviews.llvm.org/D138508



More information about the llvm-commits mailing list