[llvm] a1bd85c - [AMDGPU][GFX1013][DOC][NFC] Update assembler syntax description
Dmitry Preobrazhensky via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 13 03:45:51 PST 2022
Author: Dmitry Preobrazhensky
Date: 2022-12-13T14:44:02+03:00
New Revision: a1bd85cfc3b27fc736af35046811596a3ba13262
URL: https://github.com/llvm/llvm-project/commit/a1bd85cfc3b27fc736af35046811596a3ba13262
DIFF: https://github.com/llvm/llvm-project/commit/a1bd85cfc3b27fc736af35046811596a3ba13262.diff
LOG: [AMDGPU][GFX1013][DOC][NFC] Update assembler syntax description
Summary of changes:
- Enable register tuples with 9, 10, 11 and 12 registers (https://reviews.llvm.org/D138205).
Added:
llvm/docs/AMDGPU/gfx1013_vaddr_a5639c.rst
llvm/docs/AMDGPU/gfx1013_vaddr_c5ab43.rst
llvm/docs/AMDGPU/gfx1013_vdst_9041ac.rst
llvm/docs/AMDGPU/gfx1013_vdst_eae4c8.rst
Modified:
llvm/docs/AMDGPU/AMDGPUAsmGFX1013.rst
Removed:
llvm/docs/AMDGPU/gfx1013_vaddr_49d53a.rst
llvm/docs/AMDGPU/gfx1013_vaddr_cdc744.rst
llvm/docs/AMDGPU/gfx1013_vdst_473a69.rst
llvm/docs/AMDGPU/gfx1013_vdst_f8490d.rst
################################################################################
diff --git a/llvm/docs/AMDGPU/AMDGPUAsmGFX1013.rst b/llvm/docs/AMDGPU/AMDGPUAsmGFX1013.rst
index bfab314fea0b0..87dd73720abd6 100644
--- a/llvm/docs/AMDGPU/AMDGPUAsmGFX1013.rst
+++ b/llvm/docs/AMDGPU/AMDGPUAsmGFX1013.rst
@@ -17,7 +17,7 @@ Introduction
This document describes the syntax of *instructions specific to gfx1013*.
-For a description of other gfx1013 instructions see :doc:`Syntax of GFX10 RDNA1 Instructions<AMDGPUAsmGFX10>`.
+For a description of other gfx1013 instructions, see :doc:`Syntax of GFX10 RDNA1 Instructions<AMDGPUAsmGFX10>`.
Notation
========
@@ -40,9 +40,9 @@ MIMG
**INSTRUCTION** **DST** **SRC0** **SRC1** **MODIFIERS**
\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|\ |---|
- image_bvh64_intersect_ray :ref:`vdst<amdgpu_synid_gfx1013_vdst_f8490d>`, :ref:`vaddr<amdgpu_synid_gfx1013_vaddr_49d53a>`, :ref:`srsrc<amdgpu_synid_gfx1013_srsrc_5dafbc>` :ref:`a16<amdgpu_synid_a16>`
- image_bvh_intersect_ray :ref:`vdst<amdgpu_synid_gfx1013_vdst_f8490d>`, :ref:`vaddr<amdgpu_synid_gfx1013_vaddr_49d53a>`, :ref:`srsrc<amdgpu_synid_gfx1013_srsrc_5dafbc>` :ref:`a16<amdgpu_synid_a16>`
- image_msaa_load :ref:`vdst<amdgpu_synid_gfx1013_vdst_473a69>`, :ref:`vaddr<amdgpu_synid_gfx1013_vaddr_cdc744>`, :ref:`srsrc<amdgpu_synid_gfx1013_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
+ image_bvh64_intersect_ray :ref:`vdst<amdgpu_synid_gfx1013_vdst_9041ac>`, :ref:`vaddr<amdgpu_synid_gfx1013_vaddr_c5ab43>`, :ref:`srsrc<amdgpu_synid_gfx1013_srsrc_5dafbc>` :ref:`a16<amdgpu_synid_a16>`
+ image_bvh_intersect_ray :ref:`vdst<amdgpu_synid_gfx1013_vdst_9041ac>`, :ref:`vaddr<amdgpu_synid_gfx1013_vaddr_c5ab43>`, :ref:`srsrc<amdgpu_synid_gfx1013_srsrc_5dafbc>` :ref:`a16<amdgpu_synid_a16>`
+ image_msaa_load :ref:`vdst<amdgpu_synid_gfx1013_vdst_eae4c8>`, :ref:`vaddr<amdgpu_synid_gfx1013_vaddr_a5639c>`, :ref:`srsrc<amdgpu_synid_gfx1013_srsrc_cf7132>` :ref:`dmask<amdgpu_synid_dmask>` :ref:`dim<amdgpu_synid_dim>` :ref:`unorm<amdgpu_synid_unorm>` :ref:`glc<amdgpu_synid_glc>` :ref:`slc<amdgpu_synid_slc>` :ref:`dlc<amdgpu_synid_dlc>` :ref:`a16<amdgpu_synid_a16>` :ref:`tfe<amdgpu_synid_tfe>` :ref:`lwe<amdgpu_synid_lwe>` :ref:`d16<amdgpu_synid_d16>`
.. |---| unicode:: U+02014 .. em dash
@@ -51,7 +51,7 @@ MIMG
gfx1013_srsrc_5dafbc
gfx1013_srsrc_cf7132
- gfx1013_vaddr_49d53a
- gfx1013_vaddr_cdc744
- gfx1013_vdst_473a69
- gfx1013_vdst_f8490d
+ gfx1013_vaddr_a5639c
+ gfx1013_vaddr_c5ab43
+ gfx1013_vdst_9041ac
+ gfx1013_vdst_eae4c8
diff --git a/llvm/docs/AMDGPU/gfx1013_vaddr_49d53a.rst b/llvm/docs/AMDGPU/gfx1013_vaddr_49d53a.rst
deleted file mode 100644
index ad6e5d8075217..0000000000000
--- a/llvm/docs/AMDGPU/gfx1013_vaddr_49d53a.rst
+++ /dev/null
@@ -1,29 +0,0 @@
-..
- **************************************************
- * *
- * Automatically generated file, do not edit! *
- * *
- **************************************************
-
-.. _amdgpu_synid_gfx1013_vaddr_49d53a:
-
-vaddr
-=====
-
-Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
-
-This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
-
-*Size:* 8-12 dwords. Actual size depends on :ref:`a16<amdgpu_synid_a16>`.
-
-* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 8-12 dwords.
-* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
-
- Examples:
-
- .. parsed-literal::
-
- image_bvh_intersect_ray v[4:7], v[9:24], s[4:7]
- image_bvh_intersect_ray v[39:42], [v5, v4, v2, v1, v7, v3, v0, v6], s[12:15] a16
-
-*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1013_vaddr_a5639c.rst b/llvm/docs/AMDGPU/gfx1013_vaddr_a5639c.rst
new file mode 100644
index 0000000000000..5255dcf446f47
--- /dev/null
+++ b/llvm/docs/AMDGPU/gfx1013_vaddr_a5639c.rst
@@ -0,0 +1,19 @@
+..
+ **************************************************
+ * *
+ * Automatically generated file, do not edit! *
+ * *
+ **************************************************
+
+.. _amdgpu_synid_gfx1013_vaddr_a5639c:
+
+vaddr
+=====
+
+Image address which includes from one to four dimensional coordinates and other data used to locate a position in the image.
+
+This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
+
+*Size:* 1-12 dwords. Actual size depends on opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
+
+*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1013_vaddr_cdc744.rst b/llvm/docs/AMDGPU/gfx1013_vaddr_c5ab43.rst
similarity index 55%
rename from llvm/docs/AMDGPU/gfx1013_vaddr_cdc744.rst
rename to llvm/docs/AMDGPU/gfx1013_vaddr_c5ab43.rst
index 6a29e6eb591d4..ab27c50b5b0b8 100644
--- a/llvm/docs/AMDGPU/gfx1013_vaddr_cdc744.rst
+++ b/llvm/docs/AMDGPU/gfx1013_vaddr_c5ab43.rst
@@ -5,7 +5,7 @@
* *
**************************************************
-.. _amdgpu_synid_gfx1013_vaddr_cdc744:
+.. _amdgpu_synid_gfx1013_vaddr_c5ab43:
vaddr
=====
@@ -14,9 +14,17 @@ Image address which includes from one to four dimensional coordinates and other
This operand may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`.
-*Size:* 1-13 dwords. Actual size depends on syntax, opcode, :ref:`dim<amdgpu_synid_dim>` and :ref:`a16<amdgpu_synid_a16>`.
+*Size:* 8-12 dwords. Actual size depends on opcode and :ref:`a16<amdgpu_synid_a16>`.
-* If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
-* If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes which require more than 8 dwords for address size must specify 16 dwords due to a limited range of supported register sequences.
+
+
+ Examples:
+
+ .. parsed-literal::
+
+ image_bvh_intersect_ray v[4:7], v[9:16], s[4:7]
+ image_bvh64_intersect_ray v[5:8], v[1:12], s[8:11]
+ image_bvh_intersect_ray v[39:42], [v5, v4, v2, v1, v7, v3, v0, v6], s[12:15] a16
+ image_bvh64_intersect_ray v[39:42], [v50, v46, v23, v17, v16, v15, v21, v20, v19, v37, v40, v42], s[12:15]
*Operands:* :ref:`v<amdgpu_synid_v>`
diff --git a/llvm/docs/AMDGPU/gfx1013_vdst_f8490d.rst b/llvm/docs/AMDGPU/gfx1013_vdst_9041ac.rst
similarity index 80%
rename from llvm/docs/AMDGPU/gfx1013_vdst_f8490d.rst
rename to llvm/docs/AMDGPU/gfx1013_vdst_9041ac.rst
index 1b5b59cb5bfc9..ae36814067785 100644
--- a/llvm/docs/AMDGPU/gfx1013_vdst_f8490d.rst
+++ b/llvm/docs/AMDGPU/gfx1013_vdst_9041ac.rst
@@ -5,12 +5,12 @@
* *
**************************************************
-.. _amdgpu_synid_gfx1013_vdst_f8490d:
+.. _amdgpu_synid_gfx1013_vdst_9041ac:
vdst
====
-Image data to load by an image instruction.
+Image data to be loaded by an image instruction.
*Size:* 4 dwords.
diff --git a/llvm/docs/AMDGPU/gfx1013_vdst_473a69.rst b/llvm/docs/AMDGPU/gfx1013_vdst_eae4c8.rst
similarity index 77%
rename from llvm/docs/AMDGPU/gfx1013_vdst_473a69.rst
rename to llvm/docs/AMDGPU/gfx1013_vdst_eae4c8.rst
index 83c7f6e11da7f..198ff4c7e280c 100644
--- a/llvm/docs/AMDGPU/gfx1013_vdst_473a69.rst
+++ b/llvm/docs/AMDGPU/gfx1013_vdst_eae4c8.rst
@@ -5,16 +5,16 @@
* *
**************************************************
-.. _amdgpu_synid_gfx1013_vdst_473a69:
+.. _amdgpu_synid_gfx1013_vdst_eae4c8:
vdst
====
-Image data to load by an image instruction.
+Image data to be loaded by an image instruction.
*Size:* depends on :ref:`dmask<amdgpu_synid_dmask>`, :ref:`tfe<amdgpu_synid_tfe>` and :ref:`d16<amdgpu_synid_d16>`:
-* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits depending on :ref:`d16<amdgpu_synid_d16>`.
+* :ref:`dmask<amdgpu_synid_dmask>` may specify from 1 to 4 data elements. Each data element occupies either 32 bits or 16 bits, depending on :ref:`d16<amdgpu_synid_d16>`.
* :ref:`d16<amdgpu_synid_d16>` specifies that data elements in registers are packed; each value occupies 16 bits.
* :ref:`tfe<amdgpu_synid_tfe>` adds 1 dword if specified.
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