[PATCH] D139690: [RISCV][NFC] Define variables for vector VT list of different LMUL

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVRegisterInfo.td:516
+
+def VRNoV0 : VReg<VM1VTs, (add (sequence "V%u", 8, 31),
+                               (sequence "V%u", 1, 7)), 1>;
----------------
Wheren't we also passing `vbool` types here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D139690/new/

https://reviews.llvm.org/D139690