[PATCH] D139648: [RISCV] Use vmv.v.i for insertion into lane 0 of undef vector when profitable

[Wang Pengcheng via Phabricator via llvm-commits]

pcwang-thead added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:2838
+  Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar);
+  // We use a vmv.v.i if possible.  We limit this to LMUL2 since the work
+  // done by the vmv.v.i is linear in LMUL.  For the vmv.s.x sequence, we
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Apart from craig's concern about μ-arch implementation, LMUL>1 may increase register pressure so I limited it to LMUL<=1 in my patch, though I haven't assessed the impact of this yet :-).


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  https://reviews.llvm.org/D139648/new/

https://reviews.llvm.org/D139648