[PATCH] D139656: [RISCV] Build single element vector for start of reduction change

[Craig Topper via Phabricator via llvm-commits]

craig.topper added a comment.

Some thoughts

What if we had a a second set of VMV_S_X pseudos with LMUL1 register class, but LMUL=1,2,4,8,etc. in TSFlags for the vsetvli insertion pass to see.

We'd need a second ISD node that takes LMUL as an operand since it can't use the type. Then isel could pick the pseudo with the correct LMUL in TSFlags.

We would match the LMUL to the input type of the reduction instead of using LMUL=1.

For non-VP reductions, the VL would be the fixed width or vlmax VL. For VP, we'd still need to deal with zero vs non-zero VL to have correct behavior.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D139656/new/

https://reviews.llvm.org/D139656