[PATCH] D139656: [RISCV] Build single element vector for start of reduction change

[Philip Reames via Phabricator via llvm-commits]

reames created this revision.
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This is an alternative patch on a path to D137530 <https://reviews.llvm.org/D137530>.

The basic problem being tackled here is that we need to place a scalar into lane 0 of a vector register before our reduction instructions.  The prior scheme used a splat with VL=1, but this causes unnecessary toggles of vsetvli.  The approach taken here is to reuse the routine added in D139648 <https://reviews.llvm.org/D139648> to explicitly build a single element vector with undef high lanes.  Doing this allows us to avoid toggling VL in many cases.

This change does not contain the logic from D137530 <https://reviews.llvm.org/D137530> to perform the insert at the original VT, and then extract down to LMUL1.  We should do that as it further reduces the need for vsetvli toggles, but we can show incremental improvement without it so I left it out here.

The only potentially concerning codegen change I spot here is that we stop using a broadcast load (for VL=1) and instead do a scalar load and insert.  I think this is probably reasonable; if reviewers disagree, I can investigate using a broadcast load which writes to the under lanes. If we want to do that, we should do it for VECTOR_INSERT_ELT as well, so that'll end up as it's own patch series.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139656

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-fp.ll
  llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-int.ll
  llvm/test/CodeGen/RISCV/rvv/fold-binary-reduce.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode.ll
  llvm/test/CodeGen/RISCV/rvv/vreductions-int.ll

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