[PATCH] D139618: [AArch64][SVE][Fixed length] Fix div miscompile

[Peter Waller via Phabricator via llvm-commits]

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The prior code worked before SVE DIV was enabled 128 bit vectors.
With 128 bit vectors, when run on a 256 bit machine, it would split and
do a signed unpack, but this resulted in one full vector and one empty
vector with a half-sized predicate. The effect was that only half the
elements were treated correctly.

The fix is to bisect the vector, sign extend, do the division, truncate
and then concat.

Fixes #59357.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139618

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-fixed-length-int-rem.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-div.ll
  llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-int-rem.ll

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