[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

[Zain Jaffal via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGf9e0390751cb: [AArch64] Select SMULL for zero extended vectors when top bit is zero (authored by zjaffal).

Changed prior to commit:
  https://reviews.llvm.org/D134711?vs=475369&id=481156#toc

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711

Files:
  llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
  llvm/test/CodeGen/AArch64/aarch64-smull.ll

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