[PATCH] D134711: [AArch64] Select SMULL for zero extended vectors when top bit is zero

Florian Hahn via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Wed Dec 7 07:39:20 PST 2022

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fhahn accepted this revision.
fhahn added a comment.
This revision is now accepted and ready to land.

LGTM, thanks!


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D134711/new/

https://reviews.llvm.org/D134711

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