[PATCH] D139550: [DAGCombine] Fix always true condition in combineShiftToMULH

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon added a comment.

Looking at D133768 <https://reviews.llvm.org/D133768> it looks like you could add additional test case to dagcomb-mullohi.ll which has 2 'upper bit only' users (srl and sra)?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D139550/new/

https://reviews.llvm.org/D139550