[PATCH] D139550: [DAGCombine] Fix always true condition in combineShiftToMULH

[Juan Manuel Martinez Caamaño via Phabricator via llvm-commits]

jmmartinez created this revision.
Herald added subscribers: ecnelises, hiraditya.
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jmmartinez requested review of this revision.
Herald added a project: LLVM.
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Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139550

Files:
  llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp


Index: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -9391,7 +9391,7 @@
 
   // return true if U may use the lower bits of its operands
   auto UserOfLowerBits = [NarrowVTSize](SDNode *U) {
-    if (U->getOpcode() != ISD::SRL || U->getOpcode() != ISD::SRA) {
+    if (U->getOpcode() != ISD::SRL && U->getOpcode() != ISD::SRA) {
       return true;
     }
     ConstantSDNode *UShiftAmtSrc = isConstOrConstSplat(U->getOperand(1));


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