[PATCH] D139422: [AMDGPU] Accelerate SIRegisterInfo::getPhysRegClass

[Carl Ritson via Phabricator via llvm-commits]

critson added a comment.

In D139422#3974201 <https://reviews.llvm.org/D139422#3974201>, @arsenm wrote:

> In D139422#3974200 <https://reviews.llvm.org/D139422#3974200>, @critson wrote:
>
>> Ideally this would be a static table, but the changes required to TableGen to understand register classes for this are non-trivial.
>
> Why? The regclass structure is exactly represented there already

The register classes are represented, but there is no way to enumerate all the registers in a register class within a standard structure like GenericTable.
RegisterClass MemberList is a dag after all.
This also prevents iterating over MemberList to define some kind of mapping class between a Register and RegisterClass.

The mapping of registers to register classes is one to many, so it is also not a simple case of modifying TableGen to output a new mapping.
As far as I can tell there is no obvious rule that actually defines the base class for a given register (allocation priority and super classing are insufficient).
The best solution I can see is we extend RegisterClass to allow us to mark which classes are "base classes" and what order to enumerate them to produce a mapping table.
This functionality seems very specific to our needs, so I don't know if that is really an appropriate thing to do.


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