[PATCH] D139422: [AMDGPU] Accelerate SIRegisterInfo::getPhysRegClass

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D139422#3974200 <https://reviews.llvm.org/D139422#3974200>, @critson wrote:

> Ideally this would be a static table, but the changes required to TableGen to understand register classes for this are non-trivial.

Why? The regclass structure is exactly represented there already


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https://reviews.llvm.org/D139422