[PATCH] D139442: AMDGPU/MC: Make VReg and VISrc decoders more strict

[Petar Avramovic via Phabricator via llvm-commits]

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These are operands that use 9 bit src operand encoding
but still don't allow sgprs and inline immediates.
Report decoding fail when operands are invalid values.


https://reviews.llvm.org/D139442

Files:
  llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
  llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h
  llvm/lib/Target/AMDGPU/SIRegisterInfo.td
  llvm/lib/Target/AMDGPU/VOP3PInstructions.td
  llvm/test/MC/Disassembler/AMDGPU/decode-err.txt

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