[PATCH] D139413: [AAch64] Optimize muls with operands having enough sign bits. One operand is a sub.

[Biplob Mishra via Phabricator via llvm-commits]

bipmis created this revision.
bipmis added reviewers: dmgreen, samtebbs.
bipmis added projects: All, LLVM.
bipmis requested review of this revision.

Muls with 64bit operands where one of the operands is a register with enough sign bits
The other operand is a sub with enough sign bits.
We can generate a 32bit sub and a single smull instruction on a 32bit operand.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139413

Files:
  llvm/lib/Target/AArch64/AArch64InstrInfo.td
  llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll


Index: llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
===================================================================
--- llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
+++ llvm/test/CodeGen/AArch64/aarch64-mull-masks.ll
@@ -904,3 +904,22 @@
   %tmp3 = mul i64 %tmp1, %c
   ret i64 %tmp3
 }
+
+define i64 @smull_sext_sub(i32* %x0, i32 %x1, i16 %x2) {
+; CHECK-LABEL: smull_sext_sub:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    ldrsw x9, [x0]
+; CHECK-NEXT:    // kill: def $w2 killed $w2 def $x2
+; CHECK-NEXT:    sxth x8, w2
+; CHECK-NEXT:    sub w9, w9, w1
+; CHECK-NEXT:    smull x0, w8, w9
+; CHECK-NEXT:    ret
+entry:
+  %ext64 = load i32, i32* %x0
+  %sext = sext i32 %ext64 to i64
+  %sext2 = sext i32 %x1 to i64
+  %sext3 = sext i16 %x2 to i64
+  %sub = sub i64 %sext, %sext2
+  %mul = mul nsw i64 %sext3, %sub
+  ret i64 %mul
+}
Index: llvm/lib/Target/AArch64/AArch64InstrInfo.td
===================================================================
--- llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -800,6 +800,12 @@
   return CurDAG->ComputeNumSignBits(N->getOperand(0)) > 32 &&
          CurDAG->ComputeNumSignBits(N->getOperand(1)) > 32;
 }]>;
+def submulwithsignbits : PatFrag<(ops node:$wd, node:$ws, node:$wt),
+                                 (mul node:$wd, (sub node:$ws, node:$wt)) , [{
+  return CurDAG->ComputeNumSignBits(N->getOperand(0)) > 32 &&
+         CurDAG->ComputeNumSignBits(N->getOperand(1)->getOperand(0)) > 32 &&
+         CurDAG->ComputeNumSignBits(N->getOperand(1)->getOperand(1)) > 32;
+}]>;
 
 //===----------------------------------------------------------------------===//
 
@@ -1951,6 +1957,9 @@
           (SMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), (EXTRACT_SUBREG $Rm, sub_32), GPR64:$Ra)>;
 def : Pat<(i64 (sub GPR64:$Ra, (smullwithsignbits GPR64:$Rn, (sext GPR32:$Rm)))),
           (SMSUBLrrr (EXTRACT_SUBREG $Rn, sub_32), $Rm, GPR64:$Ra)>;
+
+def : Pat<(i64 (submulwithsignbits GPR64:$Rn, GPR64:$Rm, (sext GPR32:$Rt))),
+          (SMADDLrrr (EXTRACT_SUBREG $Rn, sub_32), (SUBSWrr (EXTRACT_SUBREG $Rm, sub_32), $Rt), XZR)>;
 } // AddedComplexity = 5
 
 def : MulAccumWAlias<"mul", MADDWrrr>;


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