[PATCH] D138529: [AVR] Optimize constant 32-bit shifts
Ben Shi via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Dec 6 00:24:31 PST 2022
benshi001 added inline comments.
================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:1861
+ size_t ShiftRegsOffset = -ShiftAmt / 8;
+ size_t ShiftBytes = Regs.size() - ShiftRegsOffset;
+ MutableArrayRef<std::pair<Register, int>> ShiftRegs =
----------------
Renaming `ShiftBytes` to `ShiftRegsSize` looks better.
================
Comment at: llvm/lib/Target/AVR/AVRISelLowering.cpp:1906
+ // with them.
+ size_t ShiftBytes = Regs.size() - (ShiftAmt / 8);
+ MutableArrayRef<std::pair<Register, int>> ShiftRegs =
----------------
Renaming `ShiftBytes` to `ShiftRegsSize` looks better.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D138529/new/
https://reviews.llvm.org/D138529
More information about the llvm-commits
mailing list