[PATCH] D139391: [RISCV] Codegen support for Zfhmin.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp:292
+                                                      &RISCV::FPR32RegClass);
+      BuildMI(MBB, MBBI, DL, get(RISCV::FCVT_S_H), SrcF32Reg)
+          .addReg(SrcReg, getKillRegState(KillSrc));
----------------
Can we use FSGNJ_S by changing the registers to their FR32 equivalent?


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td:429
+
+let Predicates = [HasStdExtZfhmin] in {
+// Floating point constant -0.0
----------------
Do we need to check NotZfh too to give priority if Zfh is also enabled?


Repository:
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  https://reviews.llvm.org/D139391/new/

https://reviews.llvm.org/D139391