[llvm] dd3fe52 - [RISCV] Remove some RISCVMatInt early exits.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2022-12-05T16:29:16-08:00
New Revision: dd3fe52492e90a67e63d9f33b5fafaeb3942066d

URL: https://github.com/llvm/llvm-project/commit/dd3fe52492e90a67e63d9f33b5fafaeb3942066d
DIFF: https://github.com/llvm/llvm-project/commit/dd3fe52492e90a67e63d9f33b5fafaeb3942066d.diff

LOG: [RISCV] Remove some RISCVMatInt early exits.

These were early exiting if we replaced a sequence with a 2 instruction
sequence since that is the best we could do. All the later optimizations
only occur if the sequence is more than 2 instructions so this wasn't a
functional check.

At best it helps the compiler generate better code, but I don't think
that was analyzed when it was added. Remove it to simplify the code.

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
index 73cfef8dad377..dc281778f0619 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMatInt.cpp
@@ -185,12 +185,8 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
     TmpSeq.emplace_back(RISCV::SLLI, TrailingZeros);
 
     // Keep the new sequence if it is an improvement.
-    if (TmpSeq.size() < Res.size()) {
+    if (TmpSeq.size() < Res.size())
       Res = TmpSeq;
-      // A 2 instruction sequence is the best we can do.
-      if (Res.size() <= 2)
-        return Res;
-    }
   }
 
   // If the constant is positive we might be able to generate a shifted constant
@@ -210,12 +206,8 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
     TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
 
     // Keep the new sequence if it is an improvement.
-    if (TmpSeq.size() < Res.size()) {
+    if (TmpSeq.size() < Res.size())
       Res = TmpSeq;
-      // A 2 instruction sequence is the best we can do.
-      if (Res.size() <= 2)
-        return Res;
-    }
 
     // Some cases can benefit from filling the lower bits with zeros instead.
     ShiftedVal &= maskTrailingZeros<uint64_t>(LeadingZeros);
@@ -224,12 +216,8 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
     TmpSeq.emplace_back(RISCV::SRLI, LeadingZeros);
 
     // Keep the new sequence if it is an improvement.
-    if (TmpSeq.size() < Res.size()) {
+    if (TmpSeq.size() < Res.size())
       Res = TmpSeq;
-      // A 2 instruction sequence is the best we can do.
-      if (Res.size() <= 2)
-        return Res;
-    }
 
     // If we have exactly 32 leading zeros and Zba, we can try using zext.w at
     // the end of the sequence.
@@ -241,12 +229,8 @@ InstSeq generateInstSeq(int64_t Val, const FeatureBitset &ActiveFeatures) {
       TmpSeq.emplace_back(RISCV::ADD_UW, 0);
 
       // Keep the new sequence if it is an improvement.
-      if (TmpSeq.size() < Res.size()) {
+      if (TmpSeq.size() < Res.size())
         Res = TmpSeq;
-        // A 2 instruction sequence is the best we can do.
-        if (Res.size() <= 2)
-          return Res;
-      }
     }
   }