[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCV.td:637
+def : ProcessorModel<"scr1-min", SCR1Model,
+                     [FeatureRV32E, FeatureStdExtC],
+                     [TuneNoDefaultUnroll]>;
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Shouldn't this also need Feature32Bit?


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D139302/new/

https://reviews.llvm.org/D139302