[PATCH] D139302: [RISCV] Add Syntacore SCR1 CPU model

[Dmitrii Petrov via Phabricator via llvm-commits]

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[RISCV] Add Syntacore SCR1 CPU model

SCR1 is available at https://github.com/syntacore/scr1

'scr1-min' corresponds to SCR1_CFG_RV32EC_MIN,
'scr1-base' corresponds to SCR1_CFG_RV32IC_BASE,
'scr1-max' corresponds to SCR1_CFG_RV32IMC_MAX.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D139302

Files:
  clang/test/Driver/riscv-cpus.c
  clang/test/Misc/target-invalid-cpu-note.c
  llvm/include/llvm/Support/RISCVTargetParser.def
  llvm/lib/Target/RISCV/RISCV.td
  llvm/lib/Target/RISCV/RISCVSchedSCR1.td

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