[PATCH] D139272: [RISCV]Keep (select c, 0/-1, X) during PerformDAGCombine

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/select-binop-identity.ll:36
+; SFB64-NEXT:  # %bb.1:
+; SFB64-NEXT:    mv a1, a2
+; SFB64-NEXT:  .LBB0_2:
----------------
liaolucy wrote:
> There is an extra instruction here, which seems to be caused by PseudoCCMOVGPR. I'll debug it more carefully, maybe a new patch is needed.
The short forward branch optimization does currently require a mv to be in shadow of the branch. Technically the hardware supports most ALU operations in the branch shadow, but that will likely require a pseudo instruction like PseudoCCMOVGPR for each ALU operation to express.


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  https://reviews.llvm.org/D139272/new/

https://reviews.llvm.org/D139272