[PATCH] D138904: [AArch64] Transform shift+and to shift+shift to select more shifted register

[Mingming Liu via Phabricator via llvm-commits]

mingmingl added a comment.

In D138904#3970087 <https://reviews.llvm.org/D138904#3970087>, @bcl5980 wrote:

> So how about this patch？

I'm not too concerned about having fewer instructions and using M pipeline, since I also concur having fewer instructions makes general sense (as you and David pointed out). So this transformation looks good to me . Also note on some aarch64 processors (e.g., neoverse n1), logical instructions with imm-shifted operand is a net win compared with two instructions; and some aarch64 processors have more than one M pipeline (neoverse n2), so fewer chances of M pipeline being a bottleneck.

Tests on microbenchmarks (llvm-test-suite, etc) might give us more confidence (the numbers depend on the specific processor though), but I don't strongly prefer a performance test.


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