[PATCH] D138904: [AArch64] Transform shift+and to shift+shift to select more shifted register

chenglin.bi via Phabricator via llvm-commits llvm-commits at lists.llvm.org
Mon Dec 5 00:45:32 PST 2022

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bcl5980 added a comment.

So how about this patch？


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  https://reviews.llvm.org/D138904/new/

https://reviews.llvm.org/D138904

Previous message: [PATCH] D133760: [VPlan] Support sinking VPScalarIVStepsRecipe.
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