[PATCH] D138766: [InstCombine] If loading from small alloca, load whole alloca and perform variable extraction

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a subscriber: reames.
lebedev.ri added a comment.

Thank you for taking a look!

In D138766#3964237 <https://reviews.llvm.org/D138766#3964237>, @spatel wrote:

> 

I remember now, that extra IR was needed to make alive2 happy,
it still has rough edges about not checking the content of pointers passed to calls,
so we have to spell the IR //somehow//..

>>> Does the 2x register limit mean we are also creating a double-width load? Are we relying on later passes/codegen to narrow that?
>>
>> We are indeed creating double-width load,
>> which is generally going to survive until Codegen.
>> Alternatively, we could produce non-canonical IR here,
>> by performing legalization ourselves.
>> Would that be better?
>
> I'm not sure it makes much difference to subsequent IR transforms, but creating a known illegal load seems like a (scary) precedent for target-independent canonicalization.
>
>>> If we're trying to justify this target-independently, then lets use a less familiar target to avoid reaching the conclusion that the transform is generally good.
>>> I have very little idea about what is happening here with RISCV64:
>>> https://godbolt.org/z/vEcMP6P4x
>>
>> Please clarify, would be be less burdensome to first proceed with
>> a single-width change, and then discuss relaxing it to double-width?
>
> Yes, the single-width seems less scary, but we're still really stretching to call this a canonicalization.



> Does transforming later in IR miss some other optimizations that you want to happen?

What does "transforming later" mean? If we don't do **this** transform,
then we are left with variable-indexed load into `alloca`,
with which we won't be able to do **anything** else,
and the entirety of the alloca won't be promoted to registers,
and now that is usually a big loss.

> For example, I'm still not sure what is happening here:
> https://godbolt.org/z/Tcq8af83j
>
> Have I messed up the target specification in some way? Assuming the 2nd version is worse, how is a target expected to reverse it?

I'm sorry, i'm not familiar with that architecture.
@craig.topper / @reames should be able to comment on that..


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