[PATCH] D138766: [InstCombine] If loading from small alloca, load whole alloca and perform variable extraction

[Roman Lebedev via Phabricator via llvm-commits]

lebedev.ri added a comment.

Thank you for taking a look!
I'm really looking forward to this change.

In D138766#3963906 <https://reviews.llvm.org/D138766#3963906>, @spatel wrote:

> I'm confused by the tests - do we care if the full load already exists? That's not part of the pattern match.

Perhaps i should adjust the tests. That was
mostly for illustrative purposes, and it stuck.

> Does the 2x register limit mean we are also creating a double-width load? Are we relying on later passes/codegen to narrow that?

We are indeed creating double-width load,
which is generally going to survive until Codegen.
Alternatively, we could produce non-canonical IR here,
by performing legalization ourselves.
Would that be better?

> If we're trying to justify this target-independently, then lets use a less familiar target to avoid reaching the conclusion that the transform is generally good.
> I have very little idea about what is happening here with RISCV64:
> https://godbolt.org/z/vEcMP6P4x

Please clarify, would be be less burdersome to first proceed with
a single-width change, and then discuss relaxing it to double-width?


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https://reviews.llvm.org/D138766