[llvm] 19d1e4c - [X86] Remove unnecessary VPERMPS/VPERMDrr overrides from znver3 model

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2022-12-01T12:30:40Z
New Revision: 19d1e4cd44e5d0999959d90df849e3de43269acf

URL: https://github.com/llvm/llvm-project/commit/19d1e4cd44e5d0999959d90df849e3de43269acf
DIFF: https://github.com/llvm/llvm-project/commit/19d1e4cd44e5d0999959d90df849e3de43269acf.diff

LOG: [X86] Remove unnecessary VPERMPS/VPERMDrr overrides from znver3 model

Reported by D138359 - the overrides matched the base class schedule definition (in the case of VPERMDYrr it was entirely replacing uses of WriteVarShuffle256 so could that could be adjusted directly)

Added: 
    

Modified: 
    llvm/lib/Target/X86/X86ScheduleZnver3.td

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/X86/X86ScheduleZnver3.td b/llvm/lib/Target/X86/X86ScheduleZnver3.td
index e7412f833a64..fb40c4cfd62b 100644
--- a/llvm/lib/Target/X86/X86ScheduleZnver3.td
+++ b/llvm/lib/Target/X86/X86ScheduleZnver3.td
@@ -1347,17 +1347,10 @@ def Zn3WriteVPERM2F128rm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
 }
 def : InstRW<[Zn3WriteVPERM2F128rm], (instrs VPERM2F128rm)>;
 
-def Zn3WriteVPERMPSYrr : SchedWriteRes<[Zn3FPVShuf]> {
-  let Latency = 7;
-  let ResourceCycles = [1];
-  let NumMicroOps = 2;
-}
-def : InstRW<[Zn3WriteVPERMPSYrr], (instrs VPERMPSYrr)>;
-
 def Zn3WriteVPERMPSYrm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
-  let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMPSYrr.Latency);
+  let Latency = !add(Znver3Model.LoadLatency, 7);
   let ResourceCycles = [1, 1, 2];
-  let NumMicroOps = !add(Zn3WriteVPERMPSYrr.NumMicroOps, 1);
+  let NumMicroOps = 3;
 }
 def : InstRW<[Zn3WriteVPERMPSYrm], (instrs VPERMPSYrm)>;
 
@@ -1375,22 +1368,15 @@ def Zn3WriteVPERMPDYmi : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
 }
 def : InstRW<[Zn3WriteVPERMPDYmi], (instrs VPERMPDYmi)>;
 
-def Zn3WriteVPERMDYrr : SchedWriteRes<[Zn3FPVShuf]> {
-  let Latency = 5;
-  let ResourceCycles = [1];
-  let NumMicroOps = 2;
-}
-def : InstRW<[Zn3WriteVPERMDYrr], (instrs VPERMDYrr)>;
-
-def Zn3WriteVPERMYm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
-  let Latency = !add(Znver3Model.LoadLatency, Zn3WriteVPERMDYrr.Latency);
+def Zn3WriteVPERMDYm : SchedWriteRes<[Zn3AGU012, Zn3Load, Zn3FPVShuf]> {
+  let Latency = !add(Znver3Model.LoadLatency, 5);
   let ResourceCycles = [1, 1, 2];
-  let NumMicroOps = !add(Zn3WriteVPERMDYrr.NumMicroOps, 0);
+  let NumMicroOps = 2;
 }
-def : InstRW<[Zn3WriteVPERMYm], (instrs VPERMQYmi, VPERMDYrm)>;
+def : InstRW<[Zn3WriteVPERMDYm], (instrs VPERMQYmi, VPERMDYrm)>;
 
 defm : Zn3WriteResYMMPair<WriteVPMOV256, [Zn3FPVShuf01], 4, [3], 2, /*LoadUOps=*/-1>; // 256-bit width packed vector width-changing move.
-defm : Zn3WriteResYMMPair<WriteVarShuffle256, [Zn3FPVShuf01], 1, [1], 2>; // 256-bit width vector variable shuffles.
+defm : Zn3WriteResYMMPair<WriteVarShuffle256, [Zn3FPVShuf], 5, [1], 2, /*LoadUOps=*/1>; // 256-bit width vector variable shuffles.
 defm : Zn3WriteResXMMPair<WriteVarVecShift, [Zn3FPVShift01], 1, [1], 1>; // Variable vector shifts.
 defm : Zn3WriteResYMMPair<WriteVarVecShiftY, [Zn3FPVShift01], 1, [1], 1>; // Variable vector shifts (YMM).
 defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; // Variable vector shifts (ZMM).