[PATCH] D138379: [VP][RISCV] Add vp.fshl/fshr and RISC-V support.

[Yeting Kuo via Phabricator via llvm-commits]

fakepaper56 added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:576
+  case Intrinsic::vp_fshr: {
+    unsigned Cost = 9;
+    auto LT = getTypeLegalizationCost(RetTy);
----------------
craig.topper wrote:
> Why 9? I only counted 7 instructions.
I am sorry it is my counting error.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138379/new/

https://reviews.llvm.org/D138379