[PATCH] D138379: [VP][RISCV] Add vp.fshl/fshr and RISC-V support.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:576
+  case Intrinsic::vp_fshr: {
+    unsigned Cost = 9;
+    auto LT = getTypeLegalizationCost(RetTy);
----------------
Why 9? I only counted 7 instructions.


================
Comment at: llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp:578
+    auto LT = getTypeLegalizationCost(RetTy);
+    if (TLI->isOperationCustom(ISD::VP_FRINT, LT.second))
+      return Cost * LT.first;
----------------
VP_FRINT?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D138379/new/

https://reviews.llvm.org/D138379